TY - JOUR ID - 2466 TI - A Simulated Annealing-based Throughput-aware Task Mapping Algorithm for Manycore Processors JO - Journal of AI and Data Mining JA - JADM LA - en SN - 2322-5211 AU - Tajary, A.R. AU - Morshedlou, H. AD - Faculty of Computer Engineering, Shahrood University of Technology, Shahrood, Iran. Y1 - 2022 PY - 2022 VL - 10 IS - 3 SP - 311 EP - 320 KW - Simulate annealing KW - Manycore processors KW - Task mapping DO - 10.22044/jadm.2022.11518.2312 N2 - With the advent of having many processor cores on a single chip in many-core processors, the demand for exploiting these on-chip resources to boost the performance of applications has been increased. Task mapping is the problem of mapping the application tasks on these processor cores to achieve lower latency and better performance. Many researches are focused on minimizing the path between the tasks that demand high bandwidth for communication. Although using these methods can result in lower latency, but at the same time, it is possible to create congestion in the network which lowers the network throughput. In this paper, a throughput-aware method is proposed that uses simulated annealing for task mapping. The method is checked on several real-world applications and simulations are conducted on a cycle-accurate network on chip simulator. The results illustrate that the proposed method can achieve higher throughput while maintaining the delay in the NoC. UR - https://jad.shahroodut.ac.ir/article_2466.html L1 - https://jad.shahroodut.ac.ir/article_2466_1281c4b25ff323922fb23d1b40c143ed.pdf ER -