Adders, as one of the major components of digital computing systems, have a strong influence on their performance. There are various types of adders, each of which uses a different algorithm to do addition with a certain delay. In addition to low computational delay, minimizing power consumption is also a main priority in adder circuit design. In this paper, the proposed adder is divided into several sub-blocks and the circuit of each sub-block is designed based on multiplexers and NOR gates to calculate the output carry or input carry of the next sub-block. This method reduces critical path delay (CPD) and therefore increases the speed of the adder. Simulation and synthesis of the proposed adder is done for cases of 8, 16, 32, and 64 bits and the results are compared with those of other fast adders. Synthesis results show that the proposed 16 and 32-bit adders have the lowest computation delay and also the best power delay product (PDP) among all recent popular adders.