A Simulated Annealing-based Throughput-aware Task Mapping Algorithm for Manycore Processors

A.R. Tajary; H. Morshedlou

Articles in Press, Accepted Manuscript, Available Online from 02 July 2022

http://dx.doi.org/10.22044/jadm.2022.11518.2312

Abstract
  With the advent of having many processor cores on a single chip in many-core processors, the demand for exploiting these on-chip resources to boost the performance of applications has been increased. Task mapping is the problem of mapping the application tasks on these processor cores to achieve lower ...  Read More

A Routing-Aware Simulated Annealing-based Placement Method in Wireless Network on Chips

A.R. Tajary; E. Tahanian

Volume 8, Issue 3 , July 2020, , Pages 409-415

http://dx.doi.org/10.22044/jadm.2020.8964.2034

Abstract
  Wireless network on chip (WiNoC) is one of the promising on-chip interconnection networks for on-chip system architectures. In addition to wired links, these architectures also use wireless links. Using these wireless links makes packets reach destination nodes faster and with less power consumption. ...  Read More